1. Field of the Invention
This invention is related generally to the field of microprocessor design and more particularly to synchronizing skip patterns and initializing the transfer buffer in a system which is configured to transfer data between two clock domains using clock skipping techniques.
2. Description of the Related Art
In simple computer systems, a single clock signal may be used to run all of the devices which are integrated into the chip. The same clock signal may be provided to a microprocessor, a memory and/or various peripheral devices. The signal is used for, among other things, clocking data transfers between the devices. This system is simple and relatively straightforward, but its simplicity can result in performance limitations. One of these limitations relates to the variations in the clock signals which are seen by the various devices on the chip. The use of a network of conductive traces to deliver the clock signal to each of the devices causes reflections, noise and other variations in the signals. These factors cause differences in the signals arriving at the different devices, which may in turn limit the devices"" ability to communicate data. For example, if there is a skew between the clock signals arriving at two devices, a value being communicated between the devices may have to be asserted by the transmitting device for a longer time than would otherwise be necessary in order to ensure that the value can be sampled by the receiving device.
Clock forwarding is one technique which can be used to minimize the impact of clock skew and allow improved performance in data transfers. In a clock forwarding scheme, the data bus and system clock which are normally used to transfer data are replaced by point-to-point data and clock signals. In other words, when data is to be transferred from one device to another, the data is transferred along with a corresponding clock signal. The data is typically clocked into a series of storage locations (e.g., flip-flops) by the transmitting device according to the forwarded clock signal. The data is then clocked out of the storage locations by the receiving device according to a local clock signal. Both of the clock signals must have the same rate, but a substantial skew in the signals will not prevent reliable transfer of the data.
While clock forwarding provides a means to transfer data between devices operating at the same clock rate, it is often desirable in modern computer systems to use different clock frequencies for different devices. For example, it may be useful to operate the core logic (i.e., the microprocessor logic) and the system logic at different frequencies. The difference in frequencies allows for advances in the performance of one type of logic without requiring equal advances in the other type of logic. Thus, for example, the processor speed can be increased without having to also speed up the system logic.
In these systems, system logic is closely tied to the system bus. As a result, the system logic usually operates at a frequency which is an integer (or half-integer) multiple of the system bus frequency. Because the system logic operates at a frequency which is a multiple of the system bus frequency, clock signals for the system logic and clock signals for the system bus can both be generated from the same reference clock. If the core logic also runs at a frequency which is an integer or half-integer multiple of the system bus frequency, it can also be easily generated. For example, if the system bus is running at 66 MHz, the system logic and core logic can be operated at 200 MHz (three times the system bus frequency). Then, if desired, the frequency of the core logic can be scaled up to 266 MHz (four times the system bus frequency), while the system logic remains at 200 MHz.
As the operating frequency of the system bus increases, however, it becomes more and more difficult to scale up the speed of the core logic because this would require a larger increase in the frequency. For example, if the system bus is running at 200 MHz and both the core logic and the system logic are running at 400 MHz, the core logic cannot be easily scaled up to 450 MHz. That is, 450 MHz is not an integer or half-integer multiple of the system bus frequency. It may therefore be useful to have multiple clocks instead of a single one. The devices which operate on a particular clock signal are within the clock domain defined by that signal.
The use of multiple clock domains in a computer system may create a number of problems which must be addressed in the system. One problem is that it is difficult to communicate between two clock domains in which the clocks are not integer or half-integer multiples of each other. This problem may be addressed by using clock skipping techniques to transfer data between the two clock domains. Implementing clock skipping in a microprocessor may be difficult, however, since it requires synchronization of the skip pattern to the clock signals in the two domains and proper initialization of the transfer buffers which are used to transfer data.
One or more of the problems described above may be solved by the various embodiments of the invention. Broadly speaking, the invention comprises a system and method for synchronizing a skip pattern to the clock signals of two clock domains and initializing the clock skipping buffer which enables data transfers between the two clock domains.
The present system is implemented in a microprocessor which has two distinct clock domains, each operating at a different clock frequency. The microprocessor is configured to transfer data from one clock domain to the other using a clock skipping buffer. Data is clocked into the buffer using the clock signal of the first clock domain, and is clocked out of the buffer using the clock signal of the second clock domain. The buffer causes pulses of the faster clock signal to be periodically skipped so that the data transferred on pulses of the faster clock signal does not overrun the data transferred on pulses of the slower clock signal.
In one embodiment, the present system comprises an alignment circuit having an alignment detector portion, a programmable delay portion and a signal offset portion. The alignment detector portion of the circuit identifies the falling edge of the clock signal in one of the clock domains that corresponds to the falling edge of a divider output signal which is locked to the reference clock by a PLL. The alignment signal is delayed for an amount of time which is programmable to correspond to the remainder of a reference clock period. The programmable delay portion of the circuit thereby produces an alignment signal which is asserted the next time the falling edges of the two clock signals are coincident. The circuit also produces a skip reset signal which is offset a predetermined number of cycles prior to the alignment signal. The skip reset signal leads the alignment signal so that the skip pattern generator can produce and apply the first skip value of the skip pattern with the assertion of the alignment signal.
One embodiment further comprises a synchronous reset circuit which is configured to produce synchronized reset signals in the two clock domains. The synchronous reset circuit accepts a primary reset signal and clocks this signal from a reference clock domain, through several intermediate steps into one of the two operating clock domains. When the reset signal has been clocked into this clock domain, the circuit delays the reset until the arrival of the next corresponding alignment signal. The reset is then transferred as logically concurrent, synchronized reset signals asserted with the respective alignment signal in each clock domain.